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https://github.com/bitcoin/bitcoin.git
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guix: replace GCC unaligned VMOV patch with binutils patch
Rather than invasively patching GCC. Given we have binutils 2.38 available, we can patch it to flip the default for `-muse-unaligned-vector-move`.
This commit is contained in:
fanquake
parent
3f6a6da3b0
commit
a0dc2ebcda
@ -110,12 +110,15 @@ desirable for building Bitcoin Core release binaries."
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(define (gcc-mingw-patches gcc)
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(package-with-extra-patches gcc
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(search-our-patches "gcc-remap-guix-store.patch"
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"vmov-alignment.patch")))
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(search-our-patches "gcc-remap-guix-store.patch")))
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(define (binutils-mingw-patches binutils)
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(package-with-extra-patches binutils
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(search-our-patches "binutils-unaligned-default.patch")))
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(define (make-mingw-pthreads-cross-toolchain target)
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"Create a cross-compilation toolchain package for TARGET"
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(let* ((xbinutils (cross-binutils target))
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(let* ((xbinutils (binutils-mingw-patches (cross-binutils target)))
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(pthreads-xlibc mingw-w64-x86_64-winpthreads)
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(pthreads-xgcc (cross-gcc target
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#:xgcc (gcc-mingw-patches mingw-w64-base-gcc)
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22
contrib/guix/patches/binutils-unaligned-default.patch
Normal file
22
contrib/guix/patches/binutils-unaligned-default.patch
Normal file
@ -0,0 +1,22 @@
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commit 6537181f59ed186a341db621812a6bc35e22eaf6
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Author: fanquake <fanquake@gmail.com>
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Date: Wed Apr 10 12:15:52 2024 +0200
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build: turn on -muse-unaligned-vector-move by default
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This allows us to avoid (more invasively) patching GCC, to avoid
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unaligned instruction use.
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diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
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index e0632681477..14a9653abdf 100644
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--- a/gas/config/tc-i386.c
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+++ b/gas/config/tc-i386.c
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@@ -801,7 +801,7 @@ static unsigned int no_cond_jump_promotion = 0;
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static unsigned int sse2avx;
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/* Encode aligned vector move as unaligned vector move. */
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-static unsigned int use_unaligned_vector_move;
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+static unsigned int use_unaligned_vector_move = 1;
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/* Encode scalar AVX instructions with specific vector length. */
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static enum
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@ -1,288 +0,0 @@
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Description: Use unaligned VMOV instructions
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Author: Stephen Kitt <skitt@debian.org>
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Bug-Debian: https://bugs.debian.org/939559
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See also: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54412
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Based on a patch originally by Claude Heiland-Allen <claude@mathr.co.uk>
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--- a/gcc/config/i386/sse.md
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+++ b/gcc/config/i386/sse.md
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@@ -1058,17 +1058,11 @@
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{
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if (FLOAT_MODE_P (GET_MODE_INNER (<MODE>mode)))
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{
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- if (misaligned_operand (operands[1], <MODE>mode))
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- return "vmovu<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}";
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- else
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- return "vmova<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}";
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+ return "vmovu<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}";
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}
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else
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{
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- if (misaligned_operand (operands[1], <MODE>mode))
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- return "vmovdqu<ssescalarsize>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}";
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- else
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- return "vmovdqa<ssescalarsize>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}";
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+ return "vmovdqu<ssescalarsize>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}";
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}
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}
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[(set_attr "type" "ssemov")
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@@ -1184,17 +1178,11 @@
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{
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if (FLOAT_MODE_P (GET_MODE_INNER (<MODE>mode)))
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{
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- if (misaligned_operand (operands[0], <MODE>mode))
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- return "vmovu<ssemodesuffix>\t{%1, %0%{%2%}|%0%{%2%}, %1}";
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- else
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- return "vmova<ssemodesuffix>\t{%1, %0%{%2%}|%0%{%2%}, %1}";
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+ return "vmovu<ssemodesuffix>\t{%1, %0%{%2%}|%0%{%2%}, %1}";
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}
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else
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{
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- if (misaligned_operand (operands[0], <MODE>mode))
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- return "vmovdqu<ssescalarsize>\t{%1, %0%{%2%}|%0%{%2%}, %1}";
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- else
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- return "vmovdqa<ssescalarsize>\t{%1, %0%{%2%}|%0%{%2%}, %1}";
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+ return "vmovdqu<ssescalarsize>\t{%1, %0%{%2%}|%0%{%2%}, %1}";
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}
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}
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[(set_attr "type" "ssemov")
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@@ -7806,7 +7794,7 @@
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"TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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"@
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%vmovlps\t{%1, %0|%q0, %1}
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- %vmovaps\t{%1, %0|%0, %1}
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+ %vmovups\t{%1, %0|%0, %1}
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%vmovlps\t{%1, %d0|%d0, %q1}"
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[(set_attr "type" "ssemov")
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(set_attr "prefix" "maybe_vex")
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@@ -13997,29 +13985,15 @@
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switch (<MODE>mode)
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{
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case E_V8DFmode:
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- if (misaligned_operand (operands[2], <ssequartermode>mode))
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- return "vmovupd\t{%2, %x0|%x0, %2}";
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- else
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- return "vmovapd\t{%2, %x0|%x0, %2}";
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+ return "vmovupd\t{%2, %x0|%x0, %2}";
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case E_V16SFmode:
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- if (misaligned_operand (operands[2], <ssequartermode>mode))
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- return "vmovups\t{%2, %x0|%x0, %2}";
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- else
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- return "vmovaps\t{%2, %x0|%x0, %2}";
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+ return "vmovups\t{%2, %x0|%x0, %2}";
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case E_V8DImode:
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- if (misaligned_operand (operands[2], <ssequartermode>mode))
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- return which_alternative == 2 ? "vmovdqu64\t{%2, %x0|%x0, %2}"
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+ return which_alternative == 2 ? "vmovdqu64\t{%2, %x0|%x0, %2}"
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: "vmovdqu\t{%2, %x0|%x0, %2}";
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- else
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- return which_alternative == 2 ? "vmovdqa64\t{%2, %x0|%x0, %2}"
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- : "vmovdqa\t{%2, %x0|%x0, %2}";
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case E_V16SImode:
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- if (misaligned_operand (operands[2], <ssequartermode>mode))
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- return which_alternative == 2 ? "vmovdqu32\t{%2, %x0|%x0, %2}"
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+ return which_alternative == 2 ? "vmovdqu32\t{%2, %x0|%x0, %2}"
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: "vmovdqu\t{%2, %x0|%x0, %2}";
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- else
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- return which_alternative == 2 ? "vmovdqa32\t{%2, %x0|%x0, %2}"
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- : "vmovdqa\t{%2, %x0|%x0, %2}";
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default:
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gcc_unreachable ();
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}
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@@ -21225,63 +21199,27 @@
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switch (get_attr_mode (insn))
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{
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case MODE_V16SF:
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- if (misaligned_operand (operands[1], <ssehalfvecmode>mode))
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- return "vmovups\t{%1, %t0|%t0, %1}";
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- else
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- return "vmovaps\t{%1, %t0|%t0, %1}";
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+ return "vmovups\t{%1, %t0|%t0, %1}";
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case MODE_V8DF:
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- if (misaligned_operand (operands[1], <ssehalfvecmode>mode))
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- return "vmovupd\t{%1, %t0|%t0, %1}";
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- else
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- return "vmovapd\t{%1, %t0|%t0, %1}";
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+ return "vmovupd\t{%1, %t0|%t0, %1}";
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case MODE_V8SF:
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- if (misaligned_operand (operands[1], <ssehalfvecmode>mode))
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- return "vmovups\t{%1, %x0|%x0, %1}";
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- else
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- return "vmovaps\t{%1, %x0|%x0, %1}";
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+ return "vmovups\t{%1, %x0|%x0, %1}";
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case MODE_V4DF:
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- if (misaligned_operand (operands[1], <ssehalfvecmode>mode))
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- return "vmovupd\t{%1, %x0|%x0, %1}";
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- else
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- return "vmovapd\t{%1, %x0|%x0, %1}";
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+ return "vmovupd\t{%1, %x0|%x0, %1}";
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case MODE_XI:
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- if (misaligned_operand (operands[1], <ssehalfvecmode>mode))
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- {
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- if (which_alternative == 2)
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- return "vmovdqu\t{%1, %t0|%t0, %1}";
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- else if (GET_MODE_SIZE (<ssescalarmode>mode) == 8)
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- return "vmovdqu64\t{%1, %t0|%t0, %1}";
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- else
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- return "vmovdqu32\t{%1, %t0|%t0, %1}";
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- }
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+ if (which_alternative == 2)
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+ return "vmovdqu\t{%1, %t0|%t0, %1}";
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+ else if (GET_MODE_SIZE (<ssescalarmode>mode) == 8)
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+ return "vmovdqu64\t{%1, %t0|%t0, %1}";
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else
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- {
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- if (which_alternative == 2)
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- return "vmovdqa\t{%1, %t0|%t0, %1}";
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- else if (GET_MODE_SIZE (<ssescalarmode>mode) == 8)
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- return "vmovdqa64\t{%1, %t0|%t0, %1}";
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- else
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- return "vmovdqa32\t{%1, %t0|%t0, %1}";
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- }
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+ return "vmovdqu32\t{%1, %t0|%t0, %1}";
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case MODE_OI:
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- if (misaligned_operand (operands[1], <ssehalfvecmode>mode))
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- {
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- if (which_alternative == 2)
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- return "vmovdqu\t{%1, %x0|%x0, %1}";
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- else if (GET_MODE_SIZE (<ssescalarmode>mode) == 8)
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- return "vmovdqu64\t{%1, %x0|%x0, %1}";
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- else
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- return "vmovdqu32\t{%1, %x0|%x0, %1}";
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- }
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+ if (which_alternative == 2)
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+ return "vmovdqu\t{%1, %x0|%x0, %1}";
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+ else if (GET_MODE_SIZE (<ssescalarmode>mode) == 8)
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+ return "vmovdqu64\t{%1, %x0|%x0, %1}";
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else
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- {
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- if (which_alternative == 2)
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- return "vmovdqa\t{%1, %x0|%x0, %1}";
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- else if (GET_MODE_SIZE (<ssescalarmode>mode) == 8)
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- return "vmovdqa64\t{%1, %x0|%x0, %1}";
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- else
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- return "vmovdqa32\t{%1, %x0|%x0, %1}";
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- }
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+ return "vmovdqu32\t{%1, %x0|%x0, %1}";
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default:
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gcc_unreachable ();
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}
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--- a/gcc/config/i386/i386.cc
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+++ b/gcc/config/i386/i386.cc
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@@ -5418,17 +5418,15 @@ ix86_get_ssemov (rtx *operands, unsigned size,
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{
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case opcode_int:
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if (scalar_mode == E_HFmode)
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- opcode = (misaligned_p
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- ? (TARGET_AVX512BW ? "vmovdqu16" : "vmovdqu64")
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- : "vmovdqa64");
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+ opcode = TARGET_AVX512BW ? "vmovdqu16" : "vmovdqu64";
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else
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- opcode = misaligned_p ? "vmovdqu32" : "vmovdqa32";
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+ opcode = "vmovdqu32";
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break;
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case opcode_float:
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- opcode = misaligned_p ? "vmovups" : "vmovaps";
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+ opcode = "vmovups";
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break;
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case opcode_double:
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- opcode = misaligned_p ? "vmovupd" : "vmovapd";
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+ opcode = "vmovupd";
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break;
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}
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}
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@@ -5438,29 +5436,21 @@ ix86_get_ssemov (rtx *operands, unsigned size,
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{
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case E_HFmode:
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if (evex_reg_p)
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- opcode = (misaligned_p
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- ? (TARGET_AVX512BW
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- ? "vmovdqu16"
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- : "vmovdqu64")
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- : "vmovdqa64");
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+ opcode = TARGET_AVX512BW ? "vmovdqu16" : "vmovdqu64";
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else
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- opcode = (misaligned_p
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- ? (TARGET_AVX512BW
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- ? "vmovdqu16"
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- : "%vmovdqu")
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- : "%vmovdqa");
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+ opcode = TARGET_AVX512BW ? "vmovdqu16" : "%vmovdqu";
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break;
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case E_SFmode:
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- opcode = misaligned_p ? "%vmovups" : "%vmovaps";
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+ opcode = "%vmovups";
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break;
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case E_DFmode:
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- opcode = misaligned_p ? "%vmovupd" : "%vmovapd";
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+ opcode = "%vmovupd";
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break;
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case E_TFmode:
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if (evex_reg_p)
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- opcode = misaligned_p ? "vmovdqu64" : "vmovdqa64";
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+ opcode = "vmovdqu64";
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else
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- opcode = misaligned_p ? "%vmovdqu" : "%vmovdqa";
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+ opcode = "%vmovdqu";
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break;
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default:
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gcc_unreachable ();
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@@ -5472,48 +5462,32 @@ ix86_get_ssemov (rtx *operands, unsigned size,
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{
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case E_QImode:
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if (evex_reg_p)
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- opcode = (misaligned_p
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- ? (TARGET_AVX512BW
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- ? "vmovdqu8"
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- : "vmovdqu64")
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- : "vmovdqa64");
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+ opcode = TARGET_AVX512BW ? "vmovdqu8" : "vmovdqu64";
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else
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- opcode = (misaligned_p
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- ? (TARGET_AVX512BW
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- ? "vmovdqu8"
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- : "%vmovdqu")
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- : "%vmovdqa");
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+ opcode = TARGET_AVX512BW ? "vmovdqu8" : "%vmovdqu";
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break;
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case E_HImode:
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if (evex_reg_p)
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- opcode = (misaligned_p
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- ? (TARGET_AVX512BW
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- ? "vmovdqu16"
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- : "vmovdqu64")
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- : "vmovdqa64");
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+ opcode = TARGET_AVX512BW ? "vmovdqu16" : "vmovdqu64";
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else
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- opcode = (misaligned_p
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- ? (TARGET_AVX512BW
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- ? "vmovdqu16"
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- : "%vmovdqu")
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- : "%vmovdqa");
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+ opcode = TARGET_AVX512BW ? "vmovdqu16" : "%vmovdqu";
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break;
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case E_SImode:
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if (evex_reg_p)
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- opcode = misaligned_p ? "vmovdqu32" : "vmovdqa32";
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+ opcode = "vmovdqu32";
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else
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- opcode = misaligned_p ? "%vmovdqu" : "%vmovdqa";
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+ opcode = "%vmovdqu";
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break;
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case E_DImode:
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case E_TImode:
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case E_OImode:
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if (evex_reg_p)
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- opcode = misaligned_p ? "vmovdqu64" : "vmovdqa64";
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+ opcode = "vmovdqu64";
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else
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- opcode = misaligned_p ? "%vmovdqu" : "%vmovdqa";
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+ opcode = "%vmovdqu";
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break;
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case E_XImode:
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- opcode = misaligned_p ? "vmovdqu64" : "vmovdqa64";
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+ opcode = "vmovdqu64";
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break;
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default:
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gcc_unreachable ();
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